US 11,922,029 B2
Modified read counter incrementing scheme in a memory sub-system
Kishore Kumar Muchherla, Fremont, CA (US); Jonathan S. Parry, Boise, ID (US); Nicola Ciocchini, Boise, ID (US); Animesh Roy Chowdhury, Boise, ID (US); Akira Goda, Tokyo (JP); Jung Sheng Hoei, Newark, CA (US); Niccolo' Righetti, Boise, ID (US); and Ugo Russo, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 12, 2022, as Appl. No. 17/863,000.
Claims priority of provisional application 63/348,399, filed on Jun. 2, 2022.
Prior Publication US 2023/0393756 A1, Dec. 7, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of memory cells; and
a processing device operatively coupled with the memory device, the processing device to:
receive a first read command at a first time, wherein the first read command is with respect to a set of memory cells of the plurality of memory cells of the memory device;
receive a second read command at a second time, wherein the second read command is with respect to the set of memory cells of the plurality of memory cells of the memory device;
increment a read counter for the memory device by a value reflecting a difference between the first time and the second time;
determine that a value of the read counter satisfies a threshold criterion; and
responsive to determining that the value of the read counter satisfies the threshold criterion, perform a data integrity scan with respect to the set of memory cells.