US 11,922,014 B2
Memory system and method
Keiri Nakanishi, Kawasaki Kanagawa (JP); Kensaku Yamaguchi, Kawasaki Kanagawa (JP); and Takashi Takemoto, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 6, 2022, as Appl. No. 17/903,636.
Prior Publication US 2023/0142767 A1, May 11, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory; and
a controller which is communicable with a host and configured to control the nonvolatile memory, wherein
the controller is configured to:
manage a first table maintaining a corresponding relationship between an address designated by the host and an address indicative of a physical position of the nonvolatile memory;
compress first data corresponding to a first address designated by a write command received from the host;
specify a size of second data obtained by compressing the first data;
determine allocation of the second data on the nonvolatile memory based on the size of the second data;
store a second address which is an address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry corresponding to the first address of entries of the first table; and
store the first address, offset information indicative of a position of a leader of the second data in the physical area, and the size of the second data in a first area of the physical area where the second data are stored.