US 11,921,786 B2
Scalable bandwidth efficient graph processing on field programmable gate arrays
Jonas Dann, Heidelberg (DE); and Daniel Ritter, Heidelberg (DE)
Assigned to SAP SE, Walldorf (DE)
Filed by SAP SE, Walldorf (DE)
Filed on May 18, 2022, as Appl. No. 17/747,922.
Prior Publication US 2023/0376534 A1, Nov. 23, 2023
Int. Cl. G06F 17/00 (2019.01); G06F 16/901 (2019.01)
CPC G06F 16/9024 (2019.01) 20 Claims
OG exemplary drawing
 
1. A system, comprising:
at least one data processor; and
at least one memory storing instructions which, when executed by the at least one data processor, cause operations comprising:
partitioning a graph into a plurality of partitions;
distributing, to each graph core of a plurality of graph cores, one or more partitions of the plurality of partitions such that each graph core executes a graph processing algorithm on one or more partitions of the plurality of partitions, the executing of the graph processing algorithm including the plurality of graph cores exchanging one or more vertex labels via a crossbar interconnecting the plurality of graph cores; and
determining, based at least on a plurality of results received from the plurality of graph cores, a result of the graph processing algorithm.