US 11,921,650 B2
Dedicated cache-related block transfer in a memory system
Liji Gopalakrishnan, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Mar. 3, 2023, as Appl. No. 18/117,119.
Application 18/117,119 is a continuation of application No. 17/581,659, filed on Jan. 21, 2022, granted, now 11,599,483.
Application 17/581,659 is a continuation of application No. 15/931,405, filed on May 13, 2020, granted, now 11,232,047, issued on Jan. 25, 2022.
Claims priority of provisional application 62/853,619, filed on May 28, 2019.
Prior Publication US 2023/0281137 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 13/1668 (2013.01) [G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cache controller circuit in a block transfer mode, the cache controller circuit comprising:
a data buffer; and
logic coupled to the data buffer, wherein the logic is to:
transfer first data to a dynamic random access memory (DRAM) device over a first data channel via a memory controller circuit;
send a block read command packet to the DRAM device via the memory controller circuit;
provide a status signal to the memory controller circuit, the status signal to indicate that a second data channel between the memory controller circuit and the DRAM device is activated to perform a data transfer with a first rank of the DRAM device on behalf of a second memory device while the first data is being transferred across the first data channel between the memory controller circuit and the DRAM device;
cause the DRAM device to enable an auxiliary data port and block read logic of the DRAM device; and
receive second data over the second data channel from the auxiliary data port; and
store the second data in the data buffer.