US 11,921,646 B2
Secure address translation services using a permission table
David Koufaty, Portland, OR (US); Rajesh Sankaran, Portland, OR (US); Anna Trikalinou, Hillsboro, OR (US); and Rupin Vakharwala, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 16, 2022, as Appl. No. 17/842,094.
Application 17/842,094 is a continuation of application No. 16/582,956, filed on Sep. 25, 2019, granted, now 11,392,511.
Prior Publication US 2022/0309008 A1, Sep. 29, 2022
Int. Cl. G06F 12/14 (2006.01); G06F 12/0862 (2016.01); G06F 12/1009 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 12/1483 (2013.01) [G06F 12/0862 (2013.01); G06F 12/1009 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/305 (2013.01); G06F 2212/6028 (2013.01); G06F 2213/0026 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a memory operable to store data;
an Input/Output Memory Management Unit (IOMMU) coupled to the memory; and
a host-to-device link coupling the IOMMU with one or more devices, wherein the IOMMU is operable as a translation agent on behalf of the one or more devices in connection with memory operations relating to the memory, including:
maintaining, by the IOMMU, a host permission table (HPT) that associates a page permission entry with each physical page of a plurality of physical pages of the memory and one or more contexts of the one or more devices on a per-bus, per-device, per-port, per-function, or per-process basis;
receiving a translated request from a discrete device of the one or more devices via the host-to-device link, wherein the translated request specifies a memory operation and a physical address within the memory pertaining to the memory operation;
determining page access permissions assigned to a context of the discrete device for a physical page of the memory within which the physical address resides by locating the page permission entry corresponding to the context of the discrete device and the physical page within the HPT;
allowing the memory operation to proceed when the page access permissions permit the memory operation; and
blocking the memory operation when the page access permissions do not permit the memory operation.