US 11,921,643 B2
Method and apparatus for dual multiplication units in a data path
Mujibur Rahman, Plano, TX (US); Timothy David Anderson, University Park, TX (US); and Soujanya Narnur, Austin, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,344.
Application 17/690,344 is a continuation of application No. 16/878,603, filed on May 20, 2020, granted, now 11,301,248.
Claims priority of provisional application 62/852,870, filed on May 24, 2019.
Prior Publication US 2022/0206802 A1, Jun. 30, 2022
Int. Cl. G06F 12/1045 (2016.01); G06F 7/24 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/53 (2006.01); G06F 7/57 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 17/16 (2006.01); H03H 17/06 (2006.01); G06F 15/78 (2006.01)
CPC G06F 12/1045 (2013.01) [G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3856 (2023.08); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); H03H 17/0664 (2013.01); G06F 9/30018 (2013.01); G06F 9/325 (2013.01); G06F 9/381 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 15/7807 (2013.01); G06F 15/781 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01)] 20 Claims
OG exemplary drawing
 
12. A method comprising:
decoding, by a processor, a first instruction including a first instruction type field indicating a dual issue instruction type;
dispatching the first instruction to a first multiplication unit and to a second multiplication unit in response to the first instruction type field indicating the dual issue instruction type;
executing the first instruction by the first multiplication unit and the second multiplication unit in a first data path of the processor;
storing, by the processor, a first result of the first instruction in a first storage location indicated by the first instruction;
decoding, by the processor, a second instruction including a second instruction type field indicating a single issue instruction type;
dispatching the second instruction to the first multiplication unit and not to the second multiplication unit in response to the second instruction type field indicating the single issue instruction type;
executing the second instruction by the first multiplication unit; and
storing, by the processor, a second result of the second instruction in a second storage location indicated by the second instruction.