US 11,921,642 B2
Methods and apparatuses for addressing memory caches
Trung Diep, San Jose, CA (US); and Hongzhong Zheng, Sunnyvale, CA (US)
Assigned to RAMBUS INC., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Nov. 14, 2022, as Appl. No. 17/986,781.
Application 17/986,781 is a continuation of application No. 17/107,831, filed on Nov. 30, 2020, granted, now 11,500,781.
Application 17/107,831 is a continuation of application No. 16/157,908, filed on Oct. 11, 2018, granted, now 10,853,261, issued on Dec. 1, 2020.
Application 16/157,908 is a continuation of application No. 15/393,232, filed on Dec. 28, 2016, granted, now 10,102,140, issued on Oct. 16, 2018.
Application 15/393,232 is a continuation of application No. 14/001,464, granted, now 9,569,359, issued on Feb. 14, 2017, previously published as PCT/US2012/026027, filed on Feb. 22, 2012.
Claims priority of provisional application 61/446,451, filed on Feb. 24, 2011.
Prior Publication US 2023/0142048 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1009 (2016.01); G06F 12/0811 (2016.01); G06F 12/0864 (2016.01); G11C 7/10 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0864 (2013.01); G11C 7/1072 (2013.01); G06F 2212/283 (2013.01); G06F 2212/656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cache memory, comprising:
cache lines on a die to store information associated with physical addresses, each physical address comprising at least first and second non-overlapping, distinct predefined portions;
separate from the cache lines, one or more tables, each table comprising table entries indexed by the first portions of respective physical addresses, wherein a respective table entry in each of the one or more tables is to store indications of whether any one or more of a plurality of cache lines have been allocated to store information;
logic circuitry coupled to the one or more tables, to output a cache hit signal upon determining that the one or more tables include a table entry, at a location within the one or more tables specified by the first portion of a specified physical address, that stores an indication that a cache line at a location in the cache lines specified by the second portion of the specified physical address, has been allocated to store information associated with the specified physical address; and
forwarding circuitry, coupled to the logic circuitry and the plurality of cache lines, to forward the information associated with the specified physical address stored in the cache line at a location in the cache lines specified by the second portion of the specified physical address after receiving the cache hit signal output by the logic circuitry.