US 11,921,635 B2
Method and apparatus for shared virtual memory to manage data coherency in a heterogeneous processing system
Altug Koker, El Dorado Hills, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 3, 2021, as Appl. No. 17/190,671.
Application 17/190,671 is a division of application No. 15/203,499, filed on Jul. 6, 2016, abandoned.
Prior Publication US 2021/0209025 A1, Jul. 8, 2021
Int. Cl. G06F 12/00 (2006.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/1009 (2013.01); G06F 12/1045 (2013.01); G06F 12/1063 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/281 (2013.01); G06F 2212/302 (2013.01); G06F 2212/608 (2013.01); G06F 2212/656 (2013.01); G06F 2212/657 (2013.01); G06F 2212/68 (2013.01); G06F 2212/682 (2013.01); G06F 2212/684 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A heterogeneous computing device comprising:
a graphics processor coupled with an application processor, wherein the graphics processor and the application processor each include a cache memory and first circuitry to perform virtual to physical memory address translation for a unified virtual memory system including a common virtual memory address space in which a complete virtual address space of the graphics processor is shared with the application processor; and
wherein the first circuitry is to manage cache coherency state concurrently with virtual to physical memory address translation for an address in the unified virtual memory system and, concurrently with an address translation associated with a write to a virtual memory address of a block of memory, the first circuitry is to:
determine coherency ownership for a cache line associated with the block of memory based on cache coherency metadata stored contiguously with virtual to physical memory address translation data for the block of memory, the coherency ownership and the virtual to physical memory address translation data determined via a single read operation that is performed based on the virtual memory address of the block of memory, wherein the block of memory is accessible to the graphics processor and the application processor via the virtual memory address; and
transfer the coherency ownership for the cache line between the graphics processor and the application processor, wherein the first circuitry of each of the graphics processor and the application processor is to transfer the coherency ownership via a response sent between the graphics processor and application processor.