US 11,921,611 B2
Synchronous hardware event collection
Thomas Norrie, Mountain View, CA (US); and Naveen Kumar, San Jose, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Jan. 7, 2022, as Appl. No. 17/571,373.
Application 17/571,373 is a continuation of application No. 16/520,558, filed on Jul. 24, 2019, granted, now 11,232,012.
Application 16/520,558 is a continuation of application No. 15/472,932, filed on Mar. 29, 2017, granted, now 10,365,987, issued on Jul. 30, 2019.
Prior Publication US 2022/0129364 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/34 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 11/36 (2006.01)
CPC G06F 11/3466 (2013.01) [G06F 9/542 (2013.01); G06F 11/302 (2013.01); G06F 11/3495 (2013.01); G06F 11/3612 (2013.01); G06F 11/348 (2013.01); G06F 2201/86 (2013.01); G06F 2201/865 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
executing a sequence of program code to perform operations using components of a processor, each component of the components having a time counter indicating a time value, wherein each time counter comprises a respective offset bit used for compensating phase variations between the time counters while performing the operations, wherein the sequence of program code comprises a first time parameter as a trigger condition for triggering a trace event across two or more components of the processor while performing the operations, and wherein one of the time counters is selected as a global time counter;
determining a global time value represented by the global time counter;
updating, based on the global time value, at least the time value represented by a corresponding time counter that is not selected as the global time counter using the respective offset bit;
determining, by comparing the time value against the first time parameter in the sequence of program code, if the trigger condition is satisfied;
in response to determining that the trigger condition is satisfied, triggering the trace event to generate event data for the two or more of the components of the processor; wherein the event data is synchronized based on the global time value; and
providing the event data to a host used to analyze the performance of the sequence of program code.