US 11,921,579 B2
Method of operating memory device, method of operating memory controller and memory system
Ki-Heung Kim, Suwon-si (KR); Jun Hyung Kim, Suwon-si (KR); Chang-Yong Lee, Hwaseong-si (KR); Sang Uhn Cha, Suwon-si (KR); and Kyung-Soo Ha, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 11, 2022, as Appl. No. 17/692,953.
Claims priority of application No. 10-2021-0092846 (KR), filed on Jul. 15, 2021.
Prior Publication US 2023/0012525 A1, Jan. 19, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method of operating a memory device, the method comprising:
receiving a first command from a controller;
activating a page of a memory cell array based on the first command;
reading data of the activated page;
detecting an error from the read data;
correcting the detected error to generate error correction data;
writing back the error correction data to the activated page based on the detected error being a single-bit error; and
controlling an error correction circuit of the memory device to receive a second command of blocking the write-back from the controller based on the detected error being a multi-bit error and to block write-back of the error correction data to the activated page based on the second command.