US 11,921,576 B2
Memory device and repair method with column-based error code tracking
Frederick A. Ware, Los Altos Hills, CA (US); and Brent Steven Haukness, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Dec. 11, 2021, as Appl. No. 17/548,509.
Application 17/548,509 is a continuation of application No. 16/790,637, filed on Feb. 13, 2020, granted, now 11,204,825.
Application 16/790,637 is a continuation of application No. 15/646,025, filed on Jul. 10, 2017, granted, now 10,565,049.
Application 15/646,025 is a continuation of application No. 14/458,546, filed on Aug. 13, 2014, granted, now 9,715,424.
Claims priority of provisional application 61/869,325, filed on Aug. 23, 2013.
Prior Publication US 2022/0171674 A1, Jun. 2, 2022
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1008 (2013.01) [G06F 11/1048 (2013.01); G06F 12/0246 (2013.01); G11C 29/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
memory core circuitry including multiple rows of data storage locations and error storage locations;
memory interface circuitry to receive a write command to activate a given row of the multiple rows of data storage locations and error storage locations; and
repair circuitry, responsive to the write command, to access error information from the error storage locations of the activated given row, the error information used to generate a comparison result for a repair operation.