US 11,921,560 B2
Memory device power management
Thomas H. Kinsley, Boise, ID (US); Baekkyu Choi, San Jose, CA (US); and Fuad Badrieh, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 19, 2022, as Appl. No. 18/084,149.
Application 18/084,149 is a continuation of application No. 17/110,140, filed on Dec. 2, 2020, granted, now 11,561,597.
Prior Publication US 2023/0118893 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3225 (2019.01)
CPC G06F 1/3225 (2013.01) 20 Claims
OG exemplary drawing
 
15. An apparatus, comprising:
a set of memory dies include a first memory die, a second memory die, and third memory die; and
a controller coupled with the set of memory dies and configured to cause the set of memory dies to:
receive, at the third memory die from a first power management circuit on the first memory die, a first operating voltage;
receiving, at the third memory die from a second power management circuit on the second memory die, a second operating voltage; and
operating the third memory die using the first operating voltage and the second operating voltage.