US 11,921,157 B2
Burn-in resilient integrated circuit for processors
Andreas H. A. Arp, Nufringen (DE); Matthias Ringe, Tuebingen (DE); Thomas Makowski, Pfullingen (DE); Michael V. Koch, Ehningen (DE); and Fatih Cilek, Boeblingen (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 7, 2021, as Appl. No. 17/467,572.
Application 17/467,572 is a continuation of application No. 16/197,868, filed on Nov. 21, 2018, granted, now 11,163,002.
Prior Publication US 2021/0396808 A1, Dec. 23, 2021
Int. Cl. G01R 31/317 (2006.01); G01R 31/00 (2006.01); H03K 5/00 (2006.01); H03K 5/133 (2014.01); H03K 19/20 (2006.01)
CPC G01R 31/31725 (2013.01) [H03K 5/133 (2013.01); G01R 31/003 (2013.01); H03K 2005/00078 (2013.01); H03K 2005/0015 (2013.01); H03K 19/20 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A burn-in resilient integrated circuit comprising:
an inverter chain;
a plurality of inverter circuits on the inverter chain, wherein a number of the plurality of inverter circuits is odd;
a plurality of sampling latches, each of the sampling latching tapping an input of the inverter circuits, respectively, such that a data input for each of the sampling latches is connected between two inverter circuits among the plurality of inverter circuits, where each of the sampling latches include a first latch and a second latch, each which are clocked to pass sampled data received from the inverter chain;
a multiplexer comprising an output pin connected to a first inverter circuit included in the inverter chain, and comprising an enable pin, a first input pin, and a second input pin; and
a local clock block comprising a clock input connected in common with the first input pin of the multiplexer such that both the clock input and the first input pin are configured to receive a common global clock signal, the local clock block including a first clock output connected to the first latch of each of the plurality of sampling latches to output a first clock signal thereto, and a second clock connected to the second latch of each of the plurality of sampling latches configured to output a second clock signal thereto;
a selectable loop that provides an electrical connection for a feedback signal from an output of the inverter chain directly to the second input pin of the multiplexer, the burn-in resilient integrated circuit configured to:
receive an engage signal at the enable pin indicating a burn-in operation is activated; and
based on receiving the engage signal indicating the burn-in operation is activated, activate the selectable loop, wherein activating the selectable loop causes the feedback signal in the burn-in resilient integrated circuit to oscillate,
wherein the burn-in resilient integrated circuit further configured to:
based on not receiving the engage signal at the enable pin indicating the burn-in operation is deactivated, deactivate the selectable loop,
wherein the feedback signal is not provided from the output of the inverter chain to the input of the inverter chain based on the selectable loop being deactivated.