| CPC H10B 43/20 (2023.02) [G11C 16/0466 (2013.01); G11C 16/06 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] | 9 Claims |
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[ 15. A nonvolatile semiconductor memory device comprising:
a substrate having a surface extending in a first direction and a second direction crossing the first direction;
a plurality of series-connected memory cell transistors, the memory cell transistors including
a first memory cell transistor,
a second memory cell transistor being provided at one side of the first memory cell transistor in a third direction crossing the first direction and the second direction,
a third memory cell transistor being provided at one side of the second memory cell transistor in the third direction, and
a fourth memory cell transistor being provided at one side of the third memory cell transistor in the third direction;
a plurality of control electrodes being stacked in the third direction, and each extending in the first direction and the second direction, the control electrodes including
a first control electrode connected to a gate of the first memory cell transistor,
a second control electrode connected to a gate of the second memory cell transistor,
a third control electrode connected to a gate of the third memory cell transistor, and
a fourth control electrode connected to a gate of the fourth memory cell transistor;
a plurality of switch elements formed on the substrate, the switch elements including
a first switch element having one end connected to the first control electrode,
a second switch element having one end connected to the second control electrode,
a third switch element having one end connected to the third control electrode, and
a fourth switch element having one end connected to the fourth control electrode;
a plurality of electric lines, the electric lines including
a first electric line having one end connected to another end of the first switch element,
a second electric line having one end connected to another end of the second switch element,
a third electric line having one end connected to another end of the third switch element, and
a fourth electric line having one end connected to another end of the fourth switch element; and
a driver circuit being connected to the electric lines, the driver circuit being configured to
apply a first voltage to the first electric line when a read operation to the second memory cell transistor is performed,
apply a second voltage to the second electric line when the read operation to the second memory cell transistor is performed,
apply a third voltage to the third electric line when the read operation to the second memory cell transistor is performed, and
apply a fourth voltage to be supplied on the fourth electric line when the read operation to the second memory cell transistor is performed,
wherein
the first voltage is higher than the second voltage,
the third voltage is higher than the first voltage and the second voltage, and
the fourth voltage is higher than the third voltage.]
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