US RE50,325 E1
3D flash memory device having dummy word lines and dummy word line voltage generators
Sang-Wan Nam, Hwaseong-si (KR); and Kitae Park, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 27, 2022, as Appl. No. 17/585,800.
Application 17/585,800 is a continuation of application No. 16/670,668, filed on Oct. 31, 2019, granted, now RE48930.
Application 15/978,230 is a continuation of application No. 15/609,761, filed on May 31, 2017, granted, now 9,984,753, issued on May 29, 2018.
Application 15/609,761 is a continuation of application No. 15/210,628, filed on Jul. 14, 2016, granted, now 9,697,901, issued on Jul. 4, 2017.
Application 15/210,628 is a continuation of application No. 14/945,354, filed on Nov. 18, 2015, abandoned.
Application 14/945,354 is a continuation of application No. 14/162,905, filed on Jan. 24, 2014, granted, now 9,812,206, issued on Nov. 7, 2017.
Application 16/670,668 is a reissue of application No. 15/978,230, filed on May 14, 2018, granted, now 10,224,105, issued on Mar. 5, 2019.
Application 17/585,800 is a reissue of application No. 15/978,230, filed on May 14, 2018, granted, now 10,224,105, issued on Mar. 5, 2019.
Claims priority of application No. 10-2013-0053212 (KR), filed on May 10, 2013.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3427 (2013.01)] 18 Claims
OG exemplary drawing
 
[ 21. A three-dimensional (3D) flash memory device comprising:
a plurality of cell strings, a cell string of the plurality of cell strings being connected between a common source line and a bit line and including a ground select transistor, at least one first dummy memory cell, a plurality of memory cells, at least one second dummy memory cell and a string select transistor being sequentially stacked along a direction perpendicular to a substrate;
wherein the ground select transistor is connected to a ground select line, the at least one first dummy memory cell is connected to at least one first dummy word line, the plurality of memory cells are connected to a plurality of word lines respectively, the at least one second dummy memory cell is connected to at least one second dummy word line respectively, the string select transistor is connected to a string select line,
wherein the ground select transistor is adjacent to the substrate and the string select transistor is adjacent to the bit line,
wherein the at least one first dummy word line is disposed between the ground select line and the plurality of word lines and adjacent to a lowermost word line of the plurality of word lines, the at least one second dummy word line is disposed between the string select line and the plurality of word lines and adjacent to an uppermost word line of the plurality of word lines,
wherein a first separation length between the ground select line and the at least one first dummy word line is different from a second separation length between the string select line and the at least one second dummy word line, and
wherein a third separation length between the ground select line and the lowermost word line is different from a fourth separation length between the string select line and the uppermost word line,
a dummy word line voltage generator configured to provide at least one first voltage to the at least one first dummy word line and provide at least one second voltage to the at least one second dummy word line during an erase operation; and
a select line voltage generator configured to generate a string select line voltage applied to the string select line and a ground select line voltage applied to the ground select line during the erase operation.]