US 12,245,529 B2
Diffusion barrier layer in programmable metallization cell
Albert Zhong, Taichung (TW); Cheng-Yuan Tsai, Chu-Pei (TW); Hai-Dang Trinh, Hsinchu (TW); and Shing-Chyang Pan, Jhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,001.
Application 17/868,824 is a division of application No. 16/807,600, filed on Mar. 3, 2020, granted, now 11,594,678, issued on Feb. 28, 2023.
Application 18/362,001 is a continuation of application No. 17/868,824, filed on Jul. 20, 2022, granted, now 11,778,931.
Prior Publication US 2023/0413696 A1, Dec. 21, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/828 (2023.02) [H10B 63/30 (2023.02); H10N 70/041 (2023.02); H10N 70/063 (2023.02); H10N 70/245 (2023.02); H10N 70/826 (2023.02); H10N 70/8416 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first conductive structure overlying a substrate;
a data storage layer disposed on the first conductive structure;
a second conductive structure overlying the data storage layer; and
a first diffusion barrier layer disposed between the data storage layer and the second conductive structure, wherein a first diffusion activation temperature of the first diffusion barrier layer is different from a second diffusion activation temperature of the second conductive structure and grain sizes of the first diffusion barrier layer are smaller than grain sizes of the second conductive structure.