US 12,245,526 B2
Sidewall protection for PCRAM device
Yu-Chao Lin, Hsinchu (TW); Yuan-Tien Tu, Chiayi County (TW); Shao-Ming Yu, Hsinchu County (TW); and Tung-Ying Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Sep. 27, 2023, as Appl. No. 18/475,978.
Application 17/839,322 is a division of application No. 16/509,105, filed on Jul. 11, 2019, granted, now 11,362,277, issued on Jun. 14, 2022.
Application 18/475,978 is a continuation of application No. 17/839,322, filed on Jun. 13, 2022, granted, now 11,818,967.
Claims priority of provisional application 62/767,372, filed on Nov. 14, 2018.
Prior Publication US 2024/0023462 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/063 (2023.02) [H10N 70/023 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell overlying an inter-metal dielectric (IMD) layer, the memory cell comprising a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode;
a protection coating on an outer sidewall of the phase change element, wherein the protection coating consists of a binary compound of carbon and hydrogen; and
a first sidewall spacer on an outer sidewall of the protection coating, the first sidewall spacer having a greater nitrogen atomic concentration than the protection coating,
wherein the protection coating forms a first interface with the phase change element, the first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.