| CPC H10N 70/011 (2023.02) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 13/0002 (2013.01); H10N 70/801 (2023.02); H10B 63/10 (2023.02)] | 29 Claims |

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1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising:
a memory cell;
a protective layer disposed along a profile of the memory cell; and
a buffer layer interposed between at least a portion of a sidewall of the memory cell and the protective layer,
wherein the memory cell includes a variable resistance layer,
wherein the buffer layer is disposed without covering a sidewall of the variable resistance layer,
wherein the sidewall of the variable resistance layer is in direct contact with the protective layer, and
wherein a density of the protective layer is greater than a density of the buffer layer.
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