US 12,245,523 B2
Quantum dot devices with fins
Jeanette M. Roberts, North Plains, OR (US); Ravi Pillarisetty, Portland, OR (US); David J. Michalak, Portland, OR (US); Zachary R. Yoscovits, Beaverton, OR (US); James S. Clarke, Portland, OR (US); and Van H. Le, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 17, 2023, as Appl. No. 18/301,439.
Application 18/301,439 is a continuation of application No. 17/592,724, filed on Feb. 4, 2022, granted, now 11,700,776.
Application 17/592,724 is a continuation of application No. 16/305,592, granted, now 11,387,399, issued on Jul. 12, 2022, previously published as PCT/US2016/036568, filed on Jun. 9, 2016.
Prior Publication US 2023/0263076 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 60/10 (2023.01); G06N 10/00 (2022.01); H10N 60/01 (2023.01); H10N 60/12 (2023.01); H10N 60/80 (2023.01)
CPC H10N 60/128 (2023.02) [G06N 10/00 (2019.01); H10N 60/0912 (2023.02); H10N 60/12 (2023.02); H10N 60/805 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A quantum dot device, comprising:
a quantum processing device; and
a non-quantum processing device,
wherein the quantum processing device includes:
a base,
a fin extending away from the base and including a quantum well layer,
a plurality of gates over the fin, wherein the plurality of gates extends away from the fin in a direction perpendicular to a longitudinal axis of the fin, and
a gate dielectric between a first gate of the plurality of gates and the fin, wherein the gate dielectric does not contact any sidewalls of the fin, and
wherein the non-quantum processing device is coupled to the quantum processing device and the non-quantum processing device is to control voltages applied to one or more of the plurality of gates during operation of the quantum processing device.