US 12,245,519 B2
Semiconductor memory device and fabrication method thereof
Chia-Chang Hsu, Kaohsiung (TW); Tang-Chun Weng, Chiayi (TW); Cheng-Yi Lin, Yilan County (TW); Yung-Shen Chen, Kaohsiung (TW); and Chia-Hung Lin, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Dec. 18, 2023, as Appl. No. 18/542,791.
Application 18/542,791 is a division of application No. 17/319,106, filed on May 13, 2021, granted, now 11,895,927.
Claims priority of application No. 202110446979.5 (CN), filed on Apr. 25, 2021.
Prior Publication US 2024/0122078 A1, Apr. 11, 2024
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor memory device, comprising:
providing a substrate comprising a conductor region thereon;
forming an interlayer dielectric layer on the substrate;
forming a conductive via in the interlayer dielectric layer, wherein the conductive via is electrically connected to the conductor region;
subjecting the interlayer dielectric layer to a first etching process, thereby forming an upper portion of the conductive via protruding from a top surface of the interlayer dielectric layer and a lower portion of the conductive via embedded in the interlayer dielectric layer;
subjecting the upper portion of the conductive via to a second etching process to trim the upper portion, wherein the upper portion has a flat top surface and a rounded edge surface extending between the flat top surface and a sidewall surface of the upper portion, after subjecting the upper portion of the conductive via to the second etching process; and
forming a storage structure conformally covering the upper portion of the conductive via.