US 12,245,517 B2
MRAM stack with reduced height
Ruilong Xie, Niskayuna, NY (US); Dimitri Houssameddine, Sunnyvale, CA (US); Kangguo Cheng, Schenectady, NY (US); Julien Frougier, Albany, NY (US); and Bruce B. Doris, Hartsdale, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 1, 2021, as Appl. No. 17/464,076.
Prior Publication US 2023/0060906 A1, Mar. 2, 2023
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10B 61/10 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A memory device comprising:
a magnetic random access memory (MRAM) stack positioned on a bottom electrode;
a metal line directly in contact with the bottom electrode;
a sidewall spacer abutting the MRAM stack; and
a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimension than the first height portion abutting an outer sidewall of the sidewall spacer on a lateral side of the sidewall spacer facing away from the MRAM stack, wherein the stepped reach through conductor connects to the metal line continuously between opposite sides of the MRAM stack and the bottom electrode.