	US 12,245,515 B2
	Interconnection for a memory array and methods for forming the same
Yu-Feng Yin, Hsinchu (TW); Min-Kun Dai, Hsinchu (TW); Chien-Hua Huang, Miaoli County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Sep. 1, 2021, as Appl. No. 17/463,985.
Claims priority of provisional application 63/175,270, filed on Apr. 15, 2021.
Prior Publication US 2022/0336733 A1, Oct. 20, 2022
Int. Cl. H10N 50/01 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)

CPC H10N 50/01 (2023.02) [H10B 61/22 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)]

20 Claims

1. A method of manufacturing a memory array device, comprising:

providing a substrate, wherein the substrate has a first region and a second region; forming an array of memory cells over the first region of the substrate, wherein each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode;

forming a memory-level dielectric layer around the array of memory cells; and

forming elongated cavities in the memory-level dielectric layer, wherein the elongated cavities expose the top electrodes of the array of memory cells;

depositing a metallic material in the elongated cavities;

forming a metal line, wherein a bottom surface of the metal line has a continuously flat portion, wherein the continuously flat portion of the bottom surface directly interfaces a respective row of top electrodes of the array of memory cells, wherein the metal line also directly interfaces a top surface of the memory-level dielectric layer.

11. A method, comprising:

forming an array of memory cells over a substrate, each of the memory cells including a bottom electrode, a magnetic tunnel junction, and a top electrode;

depositing an encapsulation layer covering the array of memory cells;

performing a planarization process, thereby exposing top electrodes of the array of memory cells from the encapsulation layer;

depositing a dielectric layer covering the top electrodes and the encapsulation layer;

forming a cavity in the dielectric layer, thereby exposing a row of the top electrodes; and

forming a metal line in the cavity, the metal line having a portion of a bottom surface that is continuously flat and physically contacting the row of the top electrodes.

17. A method, comprising: forming a dielectric cap layer over a substrate, the substrate having a memory region and a logic region, the dielectric cap layer extending from the memory region to the logic region;

forming a plurality of memory cells overlying the dielectric cap layer in the memory region, each of the memory cells including a top electrode;

forming dielectric spacers on sidewalls of the memory cells;

depositing an encapsulation layer covering the dielectric spacers and the top electrodes of the memory cells;

performing an etching process to expose the dielectric cap layer in the logic region, while the encapsulation layer in the memory region remains;

removing a portion of the encapsulation layer to expose the top electrodes of the memory cells;

depositing a dielectric layer in physical contact with the top electrodes of the memory cells in the memory region and the dielectric cap layer in the logic region, the dielectric layer covering the encapsulation layer;

forming elongated cavities in the memory-level dielectric layer, wherein the elongated cavities expose the top electrodes of the array of memory cells;

depositing a metallic material in the elongated cavities;

and forming a metal line in the elongated cavities, the metalline has a portion of a bottom surface that is continuously flat and physically contacting the top electrodes of the memory cells.