US 12,245,474 B2
Array substrate and display apparatus
Siyu Wang, Beijing (CN); Tinghua Shang, Beijing (CN); Yi Zhang, Beijing (CN); Chang Luo, Beijing (CN); Huijuan Yang, Beijing (CN); Xiaofeng Jiang, Beijing (CN); Yongjie Song, Beijing (CN); Shun Zhang, Beijing (CN); and Lulu Yang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/606,428
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Dec. 25, 2020, PCT No. PCT/CN2020/139197
§ 371(c)(1), (2) Date Oct. 25, 2021,
PCT Pub. No. WO2022/133971, PCT Pub. Date Jun. 30, 2022.
Prior Publication US 2023/0137482 A1, May 4, 2023
Int. Cl. H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a gate line;
a data line;
a voltage supply line; and
a pixel driving circuit;
wherein the pixel driving circuit comprises a plurality of transistors and a storage capacitor;
the storage capacitor comprises a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode;
the second capacitor electrode is electrically connected to the voltage supply line;
the second capacitor electrode comprises a first portion and a second portion as parts of a first unitary structure in a respective subpixel;
the voltage supply line crosses over the first portion by a first crossing-over distance;
the data line crosses over the second portion by a second crossing-over distance; and
the first crossing-over distance is greater than the second crossing-over distance;
wherein the array substrate further comprises:
an inter-layer dielectric layer between the voltage supply line and the second capacitor electrode;
a second connecting line on a side of the inter-layer dielectric layer away from the second capacitor electrode, and in a same layer as the voltage supply line and the data line;
a reset signal line on a side of the insulating layer away from the first capacitor electrode, and in a same layer as the second capacitor electrode; and
a third via extending through the inter-layer dielectric layer;
wherein the second connecting line is connected to the reset signal line through the third via.