US 12,245,466 B2
Array substrate, manufacture method thereof, display panel and display device
Wei Li, Beijing (CN); Jingjing Xia, Beijing (CN); Bin Zhou, Beijing (CN); Yang Zhang, Beijing (CN); Guangyao Li, Beijing (CN); Wei Song, Beijing (CN); Xuanang Wang, Beijing (CN); Qinghe Wang, Beijing (CN); Liusong Ni, Beijing (CN); Jun Liu, Beijing (CN); Liangchen Yan, Beijing (CN); Ming Wang, Beijing (CN); and Jingang Fang, Beijing (CN)
Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/417,334
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Nov. 5, 2020, PCT No. PCT/CN2020/126753
§ 371(c)(1), (2) Date Jun. 22, 2021,
PCT Pub. No. WO2021/093666, PCT Pub. Date May 20, 2021.
Claims priority of application No. 201911120801.0 (CN), filed on Nov. 15, 2019.
Prior Publication US 2022/0077255 A1, Mar. 10, 2022
Int. Cl. H10K 59/122 (2023.01); H10K 50/842 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/122 (2023.02) [H10K 50/8426 (2023.02); H10K 59/1213 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate;
a planarization layer on a side of the substrate;
a pixel defining layer configured to define a pixel opening region and on a side of the planarization layer away from the substrate; and
an anode in the pixel opening region and on a side of the planarization layer away from the substrate; wherein
the array substrate further comprises an intermediate insulation layer between the planarization layer and the pixel defining layer, and
the intermediate insulation layer has a chemical polarity between a chemical polarity of the planarization layer and a chemical polarity of the pixel defining layer,
the pixel defining layer has a first pixel defining region and a second pixel defining region, and a pixel opening region between the first pixel defining region and the second pixel defining region,
in the second pixel defining region, a step-shaped via hole penetrates through at least two of the intermediate insulation layer, the planarization layer, and the substrate, with the step-shaped via hole comprising a first sub-via hole in the substrate and a second sub-via hole on side of the first sub-via hole away from the substrate, an orthographic projection of the first sub-via hole on the substrate is inside an orthographic projection of the second sub-via hole on the substrate,
the anode in the second pixel defining region has a stepped shape and comprises a first anode portion on a sidewall and a bottom of the first sub-via hole, a second anode portion on a sidewall of the second sub-via hole, and a third anode portion connecting the first anode portion and the second anode portion and extending on a surface of the substrate close to the planarization layer.