US 12,245,442 B2
Semiconductor device, method of manufacturing the same and electronic device including the same
Huilong Zhu, Poughkeepsie, NY (US); Guilei Wang, Beijing (CN); Henry H. Radamson, Beijing (CN); Yanbo Zhang, Beijing (CN); and Zhengyong Zhu, Beijing (CN)
Assigned to INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Appl. No. 16/337,882
Filed by INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
PCT Filed Jul. 31, 2017, PCT No. PCT/CN2017/095178
§ 371(c)(1), (2) Date Mar. 28, 2019,
PCT Pub. No. WO2018/059109, PCT Pub. Date Apr. 5, 2018.
Claims priority of application No. 201610872541.2 (CN), filed on Sep. 30, 2016; and application No. 201710530250.X (CN), filed on Jun. 30, 2017.
Prior Publication US 2020/0027950 A1, Jan. 23, 2020
Int. Cl. H01L 21/02 (2006.01); B82Y 10/00 (2011.01); G05B 23/02 (2006.01); G06T 19/00 (2011.01); H01L 21/223 (2006.01); H01L 21/225 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/324 (2006.01); H01L 23/522 (2006.01); H04N 7/18 (2006.01); H04N 23/698 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/47 (2025.01); H10D 30/63 (2025.01); H10D 30/66 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/40 (2025.01); H10D 62/815 (2025.01); H10D 62/82 (2025.01); H10D 62/822 (2025.01); H10D 62/824 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01); G06F 3/04817 (2022.01); G06F 3/0482 (2013.01); G06V 20/40 (2022.01); H01L 21/3105 (2006.01); H04N 13/111 (2018.01); H04N 13/332 (2018.01); H04N 13/366 (2018.01); H04N 13/398 (2018.01); H04N 23/90 (2023.01)
CPC H10D 84/038 (2025.01) [B82Y 10/00 (2013.01); G05B 23/0216 (2013.01); G06T 19/006 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/2236 (2013.01); H01L 21/2252 (2013.01); H01L 21/2253 (2013.01); H01L 21/2258 (2013.01); H01L 21/3065 (2013.01); H01L 21/3083 (2013.01); H01L 21/324 (2013.01); H01L 23/5221 (2013.01); H04N 7/181 (2013.01); H04N 23/698 (2023.01); H10D 30/014 (2025.01); H10D 30/015 (2025.01); H10D 30/021 (2025.01); H10D 30/025 (2025.01); H10D 30/0291 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/477 (2025.01); H10D 30/63 (2025.01); H10D 30/668 (2025.01); H10D 30/6713 (2025.01); H10D 30/6728 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/751 (2025.01); H10D 30/797 (2025.01); H10D 62/112 (2025.01); H10D 62/116 (2025.01); H10D 62/122 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 62/371 (2025.01); H10D 62/393 (2025.01); H10D 62/40 (2025.01); H10D 62/8162 (2025.01); H10D 62/82 (2025.01); H10D 62/822 (2025.01); H10D 62/824 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/252 (2025.01); H10D 64/518 (2025.01); H10D 64/62 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/014 (2025.01); H10D 84/0149 (2025.01); H10D 84/016 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0177 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/0195 (2025.01); H10D 84/85 (2025.01); H10D 84/857 (2025.01); H10D 88/01 (2025.01); G05B 2219/32014 (2013.01); G06F 3/04817 (2013.01); G06F 3/0482 (2013.01); G06V 20/40 (2022.01); G06V 20/44 (2022.01); G06V 2201/06 (2022.01); H01L 21/31053 (2013.01); H04N 13/111 (2018.05); H04N 13/332 (2018.05); H04N 13/366 (2018.05); H04N 13/398 (2018.05); H04N 23/90 (2023.01); H10D 62/115 (2025.01); H10D 84/0172 (2025.01)] 30 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the channel layer comprises a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si;
a first leakage suppression layer and/or a first ON current enhancement layer disposed between the first source/drain layer and the channel layer and/or a second leakage suppression layer and/or a second ON current enhancement layer disposed between the channel layer and the second source/drain layer; and
a gate stack surrounding a periphery of the channel layer, wherein the gate stack is self-aligned to the channel layer, and an upper surface of the gate stack is aligned with a lower surface of the second leakage suppression layer and/or the second ON current enhancement layer, and/or a lower surface of the gate stack is aligned with an upper surface of the first leakage suppression layer and/or the first ON current enhancement layer,
wherein the second source/drain layer extends outward relative to the second leakage suppression layer and/or the second ON current enhancement layer, and/or the first source/drain layer extends outward relative to the first leakage suppression layer and/or the first ON current enhancement layer,
wherein the second leakage suppression layer and/or the second ON current enhancement layer extend or extends outward relative to the channel layer, and/or the first leakage suppression layer and/or the first ON current enhancement layer extend or extends outward relative to the channel layer, and
wherein there is a crystal interface between adjacent layers among the channel layer, either of the first leakage suppression layer or second leakage suppression layer and/or either of the first ON current enhancement layer or second ON current enhancement layer.