US 12,245,436 B2
Device structure including field effect transistors and ferroelectric capacitors
Chenchen Jacob Wang, Hsinchu (TW); Bo-Feng Young, Taipei (TW); Yu-Ming Lin, Hsinchu (TW); Chi On Chui, Hsinchu (TW); and Sai-Hooi Yeong, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/341,793.
Application 17/496,857 is a division of application No. 16/852,662, filed on Apr. 20, 2020, granted, now 11,183,504, issued on Nov. 23, 2021.
Application 18/341,793 is a continuation of application No. 17/496,857, filed on Oct. 8, 2021, granted, now 11,729,994.
Prior Publication US 2023/0345736 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 49/02 (2006.01); H01L 21/56 (2006.01)
CPC H10B 53/30 (2023.02) [H01L 23/5223 (2013.01); H01L 27/0629 (2013.01); H01L 27/0733 (2013.01); H01L 28/60 (2013.01); H01L 21/56 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric device structure comprising:
an array of field effect transistors located on a substrate;
an array of ferroelectric capacitors overlying the array of field effect transistors and comprising a respective first electrode, a respective ferroelectric material plate, and a respective second electrode, wherein each ferroelectric capacitor within the array of ferroelectric capacitors contacts a top surface of a respective gate electrode of a respective field effect transistor within the array of field effect transistors;
a first metal pad embedded in a dielectric material layer overlying the array of field effect transistors and overlying the array of ferroelectric capacitors and electrically connected to each gate electrode within the array of field effect transistors;
a second metal pad embedded in the dielectric material layer and electrically connected to each second electrode within the array of ferroelectric capacitors; and
dielectric gate spacers laterally surrounding a respective vertical stack of a gate electrode among array of field effect transistors and a ferroelectric capacitor among the array of ferroelectric capacitors.