US 12,245,433 B2
Semiconductor memory device and method of manufacturing the same
Sun Mi Park, Icheon-si (KR); Nam Kuk Kim, Icheon-si (KR); Eun Mee Kwon, Icheon-si (KR); and Sang Wan Jin, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 27, 2021, as Appl. No. 17/512,047.
Claims priority of application No. 10-2021-0062782 (KR), filed on May 14, 2021.
Prior Publication US 2022/0367485 A1, Nov. 17, 2022
Int. Cl. H10B 43/35 (2023.01); H01L 25/065 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/35 (2023.02) [H01L 25/0652 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked;
a plurality of cell plugs passing through the lower stack in a vertical direction;
an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack;
a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs;
a plurality of capping layers disposed between the plurality of cell plugs and the plurality of drain select plugs; and
a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.