US 12,245,432 B2
Memory device and manufacturing method thereof
Feng-Ching Chu, Pingtung County (TW); Feng-Cheng Yang, Zhudong Township (TW); Katherine H. Chiang, New Taipei (TW); Chung-Te Lin, Tainan (TW); and Chieh-Fang Chen, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,582.
Application 18/446,582 is a division of application No. 17/246,987, filed on May 3, 2021, granted, now 11,937,426.
Claims priority of provisional application 63/135,131, filed on Jan. 8, 2021.
Prior Publication US 2023/0389320 A1, Nov. 30, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] 20 Claims
OG exemplary drawing
 
8. A semiconductor structure, comprising:
a substrate;
a dielectric stack over the substrate, the dielectric stack comprising:
a first layer over the substrate; and
a second layer over the first layer;
a gate layer extending through the dielectric stack from top to bottom and having a cross shaped profile;
a first high-k material in direct contact with a bottom surface of the second layer and separating the gate layer from the dielectric stack; and
a channel layer conforming to an inner sidewall of the first high-k material and separating the gate layer from the first high-k material.