US 12,245,429 B2
Quasi-volatile memory with reference bit line structure
Christopher J. Petti, Mountain View, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,416.
Claims priority of provisional application 63/142,144, filed on Jan. 27, 2021.
Prior Publication US 2022/0238551 A1, Jul. 28, 2022
Int. Cl. H10B 43/27 (2023.01); G11C 11/22 (2006.01); G11C 16/26 (2006.01); H10B 43/40 (2023.01); H10B 51/20 (2023.01); H10B 51/40 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 11/2273 (2013.01); G11C 16/26 (2013.01); H10B 43/40 (2023.02); H10B 51/20 (2023.02); H10B 51/40 (2023.02)] 23 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of storage transistors including multiple strings of storage transistors arranged in parallel in a first direction with storage transistors formed along a second direction normal to the first direction, the storage transistors in each string comprising drain terminals connected to a bit line and gate terminals connected to a plurality of word lines; and
the array of storage transistors comprising a first section of strings of storage transistors for storing data, and a first string of storage transistors as a first reference string and a second string of storage transistors as a second reference string,
wherein the plurality of word lines comprises a first group of word lines and a second group of word lines, and the storage transistors in each string in the first section have gate terminals that are connected alternately to a word line in the first group and a word line in the second group; and
wherein the storage transistors in the first reference string have gate terminals connected to word lines in the first group and the storage transistors in the second reference string have gate terminals connected to word lines in the second group; and
wherein the first reference string provides a first reference bit line signal for reading stored data from the storage transistors in the first section that are connected to word lines in the second group and the second reference string provides a second reference bit line signal for reading stored data from the storage transistors in the first section that are connected to word lines in the first group.