| CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H01L 21/786 (2013.01)] | 11 Claims |
|
1. A three-dimensional AND flash memory device, comprising:
a gate stack structure located on a surface of a dielectric substrate, wherein the gate stack structure comprises a plurality of gate layers and a plurality of insulating layers alternately stacked with each other;
a first conductive pillar and a second conductive pillar extending through the gate stack structure;
an insulating pillar separating the first conductive pillar and the second conductive pillar;
a channel pillar extending through the gate stack structure; and
a charge storage structure disposed between the gate stack structure and the channel pillar, wherein the channel pillar, the first conductive pillar, the second conductive pillar and the insulating pillar are enclosed by and in the charge storage structure;
wherein the channel pillar comprises:
a first part located between the charge storage structure and the insulating pillar; and
a second part comprising a first region electrically connected to the first conductive pillar and a second region electrically connected to the second conductive pillar,
wherein the first part is connected to the second part, and a curvature of the first part is smaller than a curvature of the second part,
wherein the insulating pillar comprises a first sidewall connected to the first part and a second sidewall connected to the first conductive pillar and the second conductive pillar, and the first sidewall is connected to the second sidewall,
wherein a projection of the insulating pillar on the surface of the dielectric substrate has an entirely elliptical profile.
|