US 12,245,427 B2
Semiconductor device and method for fabricating the same
Kun Young Lee, Gyeonggi-do (KR); and Nam Kuk Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 29, 2021, as Appl. No. 17/362,152.
Claims priority of application No. 10-2021-0000902 (KR), filed on Jan. 5, 2021.
Prior Publication US 2022/0216230 A1, Jul. 7, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 27/105 (2023.01); H10B 12/00 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 12/03 (2023.02); H10B 12/30 (2023.02); H10B 12/50 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 27 Claims
OG exemplary drawing
 
1. A hybrid memory, comprising:
a substrate;
a non-volatile memory including a source line over the substrate and an alternating stack in which a plurality of insulation layers and a plurality of horizontal word lines are alternately stacked over the source line;
an opening penetrating through the alternating stack and the source line;
a volatile memory including a capacitor, the capacitor penetrating through the alternating stack,
wherein the volatile memory further includes a buried word line formed inside the substrate, a bit line disposed on the substrate,
wherein the buried word line and the bit line disposed at a lower level than the capacitor,
wherein the non-volatile memory further including a vertical channel structure penetrating through the alternating stack and the source line,
wherein the vertical channel structure comprises a channel layer penetrating through the alternating stack and the source line, and a portion of the channel layer is surrounded by the source line,
wherein the capacitor and the vertical channel structure are disposed within the opening,
wherein an outer wall of the capacitor is spaced apart from an inner wall of the opening, and
wherein the vertical channel structure covers a portion of a bottom surface of the opening.