US 12,245,426 B2
Staircase formation in a memory array
Alyssa N. Scarbrough, Boise, ID (US); Lifang Xu, Boise, ID (US); and Jordan D. Greenlee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 26, 2022, as Appl. No. 17/822,712.
Prior Publication US 2024/0071502 A1, Feb. 29, 2024
Int. Cl. H10B 43/20 (2023.01); G11C 16/08 (2006.01); H01L 21/768 (2006.01); H10B 43/35 (2023.01)
CPC H10B 43/20 (2023.02) [H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 21/76885 (2013.01); H10B 43/35 (2023.02); G11C 16/08 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a first liner material within a cavity of a set of stacked materials comprising alternating dielectric material and sacrificial material;
depositing a second liner material within the cavity to at least partially overlay the first liner material;
removing some of the second liner material and leaving a doped portion of the second liner material that overlays a doped portion of the first liner material;
removing some of the first liner material and leaving the doped portion of the first liner material that overlays a first contact surface of a first sacrificial layer of the sacrificial material;
exposing a second contact surface of a second sacrificial layer of the sacrificial material that is below the first sacrificial layer;
exposing a third contact surface of a third sacrificial layer of the sacrificial material that is below the second sacrificial layer;
replacing the sacrificial material with metal material; and
forming a first conductive pillar above a first contact surface of a first metal layer that replaced the first sacrificial layer, a second conductive pillar above a second contact surface of a second metal layer that replaced the second sacrificial layer, and a third conductive pillar above a third contact surface of a third metal layer that replaced the third sacrificial layer.