US 12,245,424 B2
One-time programmable memory capacitor structure and manufacturing method thereof
Kuo-Hsing Lee, Hsinchu County (TW); Po-Wen Su, Kaohsiung (TW); Chien-Liang Wu, Tainan (TW); and Sheng-Yuan Hsueh, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORPORATION, Hsinchu (TW)
Filed by UNITED MICROELECTRONICS CORPORATION, Hsinchu (TW)
Filed on Dec. 7, 2021, as Appl. No. 17/543,757.
Claims priority of application No. 202111313571.7 (CN), filed on Nov. 8, 2021.
Prior Publication US 2023/0147512 A1, May 11, 2023
Int. Cl. H10B 20/25 (2023.01); H01L 49/02 (2006.01)
CPC H10B 20/25 (2023.02) [H01L 28/75 (2013.01); H01L 28/92 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A one-time programmable memory (OTP memory) capacitor structure, comprising:
a semiconductor substrate;
a bottom electrode, provided on the semiconductor substrate;
a capacitor insulating layer, provided on the bottom electrode; and
a metal electrode stack structure, comprising a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence, wherein the metal layer is provided on the capacitor insulating layer and is used as a top electrode, and the insulating sacrificial layer is provided between the metal layer and the capping layer, wherein the side walls of the metal layer, the side walls of the insulating sacrificial layer and the side walls of the capping layer are on the same plane.