US 12,245,418 B1
Semiconductor structure integrating logic element and memory element
Chun-Ming Lin, Hsinchu County (TW)
Filed by Chun-Ming Lin, Hsinchu County (TW)
Filed on Oct. 30, 2024, as Appl. No. 18/931,868.
Int. Cl. H01L 27/22 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/775 (2006.01); H10B 12/00 (2023.01); H10B 43/30 (2023.01); H10B 80/00 (2023.01)
CPC H10B 12/30 (2023.02) [H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/775 (2013.01); H10B 43/30 (2023.02); H10B 80/00 (2023.02)] 25 Claims
OG exemplary drawing
 
1. A semiconductor structure integrating a logic element and a memory element, comprising:
a substrate, having a first region and a second region laterally adjacent to the first region;
a logic element, disposed in the first region of the substrate, the logic element comprising a plurality of transistors; and
a memory element, disposed in the second region of the substrate, the memory element comprising:
a lower electrode, disposed above the substrate, the lower electrode comprising a first metal layer and a first copper-phosphorus alloy layer, wherein the first copper-phosphorus alloy layer extends along a contour of the first metal layer to surround the first metal layer;
a upper electrode, disposed above the substrate and the lower electrode, the upper electrode comprising a second metal layer and a second copper-phosphorus alloy layer, wherein the second copper-phosphorus alloy layer extends along a contour of the second metal layer to surround the second metal layer; and
a dielectric layer, disposed between the upper electrode and the lower electrode.