| CPC H10B 12/20 (2023.02) [G11C 11/404 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] | 11 Claims |
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1. A semiconductor-element-including memory device that is a memory device in which in plan view on a substrate, a plurality of pages are arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction,
each memory cell included in each page comprising:
a semiconductor body that stands on the substrate in a vertical direction relative to the substrate or that extends along the substrate in a horizontal direction relative to the substrate;
a first impurity layer and a second impurity layer that are disposed at respective ends of the semiconductor body;
a first gate insulator layer that partially or entirely surrounds a side surface of the semiconductor body between the first impurity layer and the second impurity layer and that is in contact with or in close vicinity to the first impurity layer;
a second gate insulator layer that surrounds the side surface of the semiconductor body, that is connected to the first gate insulator layer, and that is in contact with or in close vicinity to the second impurity layer;
a first gate conductor layer that partially or entirely covers the first gate insulator layer;
a second gate conductor layer that covers the second gate insulator layer; and
a channel semiconductor layer that is the semiconductor body and that is covered by the first gate insulator layer and the second gate insulator layer, wherein
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside the channel semiconductor layer,
in a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage that is higher than the voltage of either the first impurity layer or the second impurity layer or that is higher than the voltages of both the first impurity layer and the second impurity layer,
in a page erase operation, the group of positive holes are discharged through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer by controlling the voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer, and the voltage of the channel semiconductor layer is made equal to a second data retention voltage that is lower than the first data retention voltage,
the first impurity layer of each memory cell is connected to a corresponding one of source lines, the second impurity layer thereof is connected to a corresponding one of bit lines, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a corresponding one of word lines, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a corresponding one of plate lines,
the source lines, the word lines, and the plate lines are disposed parallel to the pages in plan view,
the bit lines are disposed in a direction perpendicular to the pages, and
in the page erase operation, an erase voltage is applied to a page, among the pages, for which selective erasing is performed, and a ground voltage is applied to a non-selected page among the pages.
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