| CPC H10B 12/053 (2023.02) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] | 16 Claims |
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1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising an isolation region, an active region adjacent to the isolation region and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material, wherein etching rates between the dielectric material filled in the isolation trench and the gate electrode material filled in the gate trench are different;
after filling the dielectric material in the isolation trench and filing the gate electrode material in the gate trench, forming a hard mask on the first top surface of the substrate to expose the dielectric material filled in the isolation trench and the gate electrode material filled in the gate trench;
after forming the hard mask on the first top surface of the substrate, performing an etching process to remove top portions of the dielectric material and the gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material; and
depositing a gate conductive material to cover the dielectric material and the gate electrode material,
wherein the second top surface of the dielectric material and the third top surface of the gate electrode material are substantially at a same level and are substantially lower than the first top surface of the substrate.
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