| CPC H10B 10/125 (2023.02) | 27 Claims |
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1. A semiconductor device comprising:
a semiconductor substrate;
multiple conductive layers vertically stacked along a vertical direction on the semiconductor substrate, the multiple conductive layers comprising a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together; and
multiple transistors comprising a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer, each transistor comprising a first terminal, a second terminal, and a gate terminal,
wherein first terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer, and
wherein the multiple transistors further comprise: another second transistor in the third conductive layer, and wherein the first transistor and the third transistor are transistors of a first dopant type, and the second transistor and the another second transistor are transistors of a second dopant type that is different from the first dopant type.
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21. A semiconductor device comprising:
a semiconductor substrate;
multiple conductive layers vertically stacked on the semiconductor substrate comprising a bottom conductive layer, a middle conductive layer, and a top conductive layer that are sequentially stacked together;
a first semiconductor pillar vertically penetrating through the multiple conductive layers onto the semiconductor substrate, the first semiconductor pillar comprising a first bottom portion surrounded by the bottom conductive layer, a first middle portion surrounded by the middle conductive layer, and a first top portion surrounded by the top conductive layer;
a second semiconductor pillar vertically penetrating through the multiple conductive layers onto the semiconductor substrate, the second semiconductor pillar comprising a second bottom portion surrounded by the bottom conductive layer, a second middle portion surrounded by the middle conductive layer, and a second top portion surrounded by the top conductive layer; and
a plurality of gate dielectric structures comprising a first gate dielectric structure surrounded by the first bottom portion and the bottom conductive layer and a second gate dielectric structure surrounded by the first top portion and the top conductive layer,
wherein the first middle portion of the first semiconductor pillar is conductively coupled to the middle conductive layer,
wherein the semiconductor substrate comprises a first region having a first dopant type and a second region having a second dopant type different from the first dopant type, wherein the first semiconductor pillar vertically extends onto the first region to form first junctions with the first dopant type, and the second semiconductor pillar vertically extends onto the second region to form second junctions with the second dopant type, and
wherein each of the first top portion and the first middle portion of the first semiconductor pillar is configured to be a corresponding first junction and is doped with a first material having the first dopant type, and each of the second top portion and the second middle portion is configured to be a corresponding second junction and is doped with a second material having the second dopant type.
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