| CPC H10B 10/12 (2023.02) [H01L 21/321 (2013.01); H01L 21/76838 (2013.01); H01L 23/5283 (2013.01); H01L 27/0207 (2013.01)] | 20 Claims |

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1. A device, comprising:
a first gate electrode corresponding to transistors of a memory cell;
a second gate electrode separated from the first gate electrode and corresponding to the transistors;
a word line coupled to the memory cell and located between the first gate electrode and the second gate electrode; and
a first metal island configured to couple a first power supply to the memory cell,
wherein, along a first direction, a first boundary of the first metal island is located between a first boundary of the first gate electrode and a second boundary of the first gate electrode and is located between a first boundary of the word line and a second boundary of the word line, and
along the first direction, each of the first boundary of the first gate electrode and the first boundary of the word line is located between the first boundary of the first metal island and a second boundary of the first metal island.
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