US 12,245,383 B2
Method of preparing a high density interconnect printed circuit board including microvias filled with copper
Bert Reents, Berlin (DE); Akif Özkök, Berlin (DE); Soungsoo Kim, Berlin (DE); Horst Brüggmann, Berlin (DE); Herwig Josef Berthold, Berlin (DE); Marcin Klobus, Berlin (DE); Thomas Schiwon, Berlin (DE); and Marko Mirkovic, Berlin (DE)
Assigned to Atotech Deutschland GmbH & Co. KG, Berlin (DE)
Appl. No. 17/636,502
Filed by Atotech Deutschland Gmbh & Co. KG, Berlin (DE)
PCT Filed Aug. 19, 2020, PCT No. PCT/EP2020/073186
§ 371(c)(1), (2) Date Feb. 18, 2022,
PCT Pub. No. WO2021/032776, PCT Pub. Date Feb. 25, 2021.
Claims priority of application No. 19192196 (EP), filed on Aug. 19, 2019.
Prior Publication US 2022/0279662 A1, Sep. 1, 2022
Int. Cl. H05K 3/42 (2006.01); C25D 3/38 (2006.01); C25D 5/02 (2006.01); C25D 5/18 (2006.01); C25D 5/34 (2006.01); C25D 5/48 (2006.01); C25D 7/00 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H05K 3/10 (2006.01); H05K 3/46 (2006.01); H05K 3/18 (2006.01)
CPC H05K 3/425 (2013.01) [C25D 3/38 (2013.01); C25D 5/022 (2013.01); C25D 5/18 (2013.01); C25D 5/34 (2013.01); C25D 5/48 (2013.01); C25D 7/00 (2013.01); H01L 21/4857 (2013.01); H01L 21/76877 (2013.01); H05K 3/108 (2013.01); H05K 3/423 (2013.01); H05K 3/429 (2013.01); H05K 3/4623 (2013.01); H05K 3/181 (2013.01); H05K 2203/0353 (2013.01); H05K 2203/072 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/1492 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method of preparing a high density interconnect printed circuit board (HDI PCB) including microvias filled with copper, the method comprising the steps of:
a1) providing a multi-layer substrate (10) comprising
(i) a stack assembly of an electrically conductive interlayer (14) embedded between two insulating layers (12) having a peripheral surface,
(ii) a conductive cover layer (16, 16a, 16b) covering the peripheral surface of the insulating layers (12) of the multi-layer substrate (10), and
(iii) a microvia (20) extending from the peripheral surface of the multi-layer substrate (10) through the conductive cover layer (16, 16a, 16b) and ending on the conductive interlayer (14);
b1) depositing a conductive layer (30) on the cover layer (16a, 16b) and on an inner surface of the microvia (20);
c) electrodepositing a copper filling (42) in the microvia (20) and a first copper layer (40) on the conductive layer (30) wherein a thickness of the first copper layer (40) is from 0.1 to 3 μm and wherein the copper filling (42) and the first copper layer (40) form together a planar surface (32), and
further comprising subsequent to step c):
d) forming a patterned masking film (50) on the first copper layer (40);
e) electrodepositing a second copper layer (60) in the area not covered by the patterned masking film (50);
f) removing the patterned masking film (50), and
g1) etching the peripheral surface of the processed multi-layer substrate (10) provided under a1) and b1) for an etching time sufficient to completely remove only the first copper layer (40), the conductive layer (30) and the conductive cover layer (16, 16a, 16b) in the areas which were covered by the masking film (50) in step d), and the etching time does not result in trace-to-trace narrowing and does not result in undercut etching.