US 12,245,377 B2
Component carrier with embedded semiconductor component and embedded highly-conductive block which are mutually coupled
Johannes Stahr, St. Lorenzen im Mürztal (AT); Andreas Zluc, Leoben (AT); Mike Morianz, Graz (AT); and Heinz Moitzi, Zeltweg (AT)
Filed by AT&S Austria Technologie & Systemtechnik Aktiengesellschaft, Leoben (AT)
Filed on Oct. 10, 2022, as Appl. No. 18/045,256.
Application 18/045,256 is a continuation in part of application No. 16/827,193, filed on Mar. 23, 2020, granted, now 11,495,513.
Claims priority of application No. 19166119 (EP), filed on Mar. 29, 2019.
Prior Publication US 2023/0055435 A1, Feb. 23, 2023
Int. Cl. H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/40 (2006.01)
CPC H05K 1/186 (2013.01) [H05K 1/0204 (2013.01); H05K 1/0209 (2013.01); H05K 1/115 (2013.01); H05K 3/4038 (2013.01); H05K 2201/0364 (2013.01); H05K 2201/064 (2013.01); H05K 2201/096 (2013.01); H05K 2201/10416 (2013.01); H05K 2203/1131 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A component carrier, comprising:
a stack comprising at least one horizontal electrically conductive layer structure and at least one electrically insulating layer structure;
a semiconductor component embedded in the stack;
at least one vertical via being laterally offset from the semiconductor component;
wherein the at least one horizontal electrically conductive layer structure electrically connects the vertical via to a bottom main surface of the semiconductor component;
a highly-conductive block embedded in the stack below the semiconductor component and being thermally and/or electrically coupled with the semiconductor component, wherein the horizontal electrically conductive layer structure is arranged between the bottom main surface of the semiconductor component and the highly-conductive block;
wherein the component carrier is configured for a current flow from the vertical via to the horizontal electrically conductive layer structure, from the horizontal electrically conductive layer structure to the highly conductive block, and from the highly conductive block to the bottom main surface of the semiconductor component, from the bottom main surface of the semiconductor component to an upper main surface of the semiconductor component, and from the upper surface of the semiconductor component to the outside of the component carrier.