| CPC H04W 74/0833 (2013.01) [H04W 74/006 (2013.01)] | 20 Claims | 

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               1. A first node, comprising: 
            at least one processor; and 
                one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause the first node to perform operations comprise: 
                receiving first signaling, wherein the first signaling indicates a plurality of physical random access channel occasion groups, and each of the plurality of physical random access channel occasion groups comprises a plurality of physical random access channel occasions; and 
                receiving second signaling, wherein the second signaling indicates a value of a first index, and the value of the first index corresponds to at least one corresponding physical random access channel occasion group of the plurality of physical random access channel occasion groups, wherein the value of the first index corresponds to a first physical random access channel occasion index, the first physical random access channel occasion index indicates a first physical random access channel occasion, and a first physical random access channel occasion group is indicated by the first physical random access channel occasion and a first occasion number, wherein the first occasion number is a corresponding number of {2, 4, 8}. 
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