US 12,245,252 B2
Default PDSCH beam setting and PDCCH prioritization for multi panel reception
Bishwarup Mondal, San Ramon, CA (US); Avik Sengupta, San Jose, CA (US); and Alexei Davydov, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 5, 2024, as Appl. No. 18/405,783.
Application 18/405,783 is a continuation of application No. 17/175,375, filed on Feb. 12, 2021, granted, now 11,902,985.
Claims priority of provisional application 62/976,953, filed on Feb. 14, 2020.
Prior Publication US 2024/0284467 A1, Aug. 22, 2024
Int. Cl. H04W 72/23 (2023.01); H04W 72/56 (2023.01); H04W 72/0453 (2023.01)
CPC H04W 72/23 (2023.01) [H04W 72/56 (2023.01); H04W 72/0453 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for use in a user equipment (UE), wherein the apparatus comprises:
memory to store:
a first value that indicates a first control resource set (CORESET) of a plurality of CORESETs, wherein the first CORESET has a first characteristic; and
a second value that indicates a second CORESET of the plurality of CORESETs, wherein the second CORESET has a second characteristic;
wherein the first value is different than the second value; and
wherein the first CORESET is associated with a first downlink (DL) bandwidth part (BWP) and the second CORESET is associated with a second DL BWP; and
one or more processors configured to:
monitor, on the first DL BWP, for a first downlink channel in a CORESET of the plurality of CORESETs that has the first characteristic; and
monitor, on the second DL BWP, for a second downlink channel in a CORESET of the plurality of CORESETs that has the second characteristic.