US 12,245,238 B2
Uplink control information multiplexing
Yi Huang, San Diego, CA (US); Wanshi Chen, San Diego, CA (US); Peter Gaal, San Diego, CA (US); Tingfang Ji, San Diego, CA (US); Wei Yang, San Diego, CA (US); Gokul Sridharan, Sunnyvale, CA (US); and Ahmed Elshafie, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 6, 2022, as Appl. No. 17/647,273.
Claims priority of provisional application 63/137,009, filed on Jan. 13, 2021.
Prior Publication US 2022/0225381 A1, Jul. 14, 2022
Int. Cl. H04W 72/1263 (2023.01); H04L 27/26 (2006.01); H04W 72/21 (2023.01); H04W 72/566 (2023.01)
CPC H04W 72/21 (2023.01) [H04L 27/2607 (2013.01); H04W 72/1263 (2013.01); H04W 72/566 (2023.01)] 28 Claims
OG exemplary drawing
 
1. A user equipment (UE) for wireless communication, comprising:
one or more memories; and
one or more processors coupled to the one or more memories, the one or more processors configured to:
generate an uplink control information (UCI) message including a scheduling request bit multiplexed with a first UCI bit and a second UCI bit, including:
selection of a set of sequences, of a set of candidate sets of sequences, to use for multiplexing the first UCI bit and the second UCI bit, the selection of the set of sequences indicating the scheduling request bit, wherein the set of sequences includes a first sequence and a second sequence that is orthogonal to the first sequence, and
multiplexing of the first UCI bit and the second UCI bit based at least in part on the set of sequences by applying the first sequence to the first UCI bit and applying the second sequence to the second UCI bit;
wherein the first UCI bit having the first sequence applied is superimposed with the second UCI bit having the second sequence applied; and
transmit the UCI message.