| CPC H04W 72/1263 (2013.01) [H04L 5/0012 (2013.01); H04L 5/0044 (2013.01); H04W 72/0446 (2013.01); H04W 72/20 (2023.01)] | 16 Claims |

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1. An apparatus comprising:
at least one memory element; and
processing circuitry coupled to the at least one memory element, the processing circuitry configured to:
transmit a control message indicating downlink transmission resources allocated for a plurality of payload data messages, wherein the control message includes an indication of respective time-domain resources allocated to each of the payload data messages, wherein the indication includes:
an index to a table of resource assignments, wherein the index indicates a first entry of the table, the first entry identifying the respective time-domain resources allocated to at least a first of the payload data messages; and
at least one offset value that identifies a second entry of the table by identifying the position of the second entry relative to the first entry, the second entry identifying the respective time-domain resources allocated to at least a second of the payload data messages, wherein the at least one offset value is distinct from the index; and
transmit the plurality of payload data messages according to the allocated downlink transmission resources.
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