| CPC H04W 56/001 (2013.01) [H04L 1/1642 (2013.01); H04W 24/10 (2013.01); H04W 76/30 (2018.02)] | 30 Claims |

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1. An apparatus for wireless communications at a user equipment (UE), comprising:
a processor;
memory coupled with the processor; and
instructions stored in the memory and executable by the processor to cause the apparatus to:
receive, from a serving cell operating on a first frequency, an indication that synchronization signal block (SSB) indexes of a target cell operating on a second frequency can be derived from timing of the serving cell; and
derive an SSB index of the target cell, based on the timing of the serving cell.
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