US 12,244,835 B2
Image processing device and image processing method
Masaru Ikeda, Tokyo (JP); and Jongdae Kim, Kanagawa (JP)
Assigned to SONY GROUP CORPORATION, Tokyo (JP)
Appl. No. 17/635,384
Filed by Sony Group Corporation, Tokyo (JP)
PCT Filed Sep. 18, 2020, PCT No. PCT/JP2020/035428
§ 371(c)(1), (2) Date Feb. 15, 2022,
PCT Pub. No. WO2021/054438, PCT Pub. Date Mar. 25, 2021.
Claims priority of provisional application 62/903,210, filed on Sep. 20, 2019.
Prior Publication US 2022/0345733 A1, Oct. 27, 2022
Int. Cl. H04N 19/33 (2014.01); H04N 19/174 (2014.01); H04N 19/426 (2014.01)
CPC H04N 19/33 (2014.11) [H04N 19/174 (2014.11); H04N 19/426 (2014.11)] 5 Claims
OG exemplary drawing
 
1. An image processing device comprising:
processing circuitry configured to decode a bitstream to generate an image according to an encoding standard in which a horizontal size of one tile is restricted by a restriction value, wherein the restriction value is enabled by a flag in the bitstream,
wherein the restriction value is set according to each level that defines maximum resolution and frame rate and the following equation (1) using a maximum value MaxLumaPs of the number of luminance picture samples

OG Complex Work Unit Math