US 12,244,683 B2
Serial data receiver with even/odd mismatch compensation
Ryan D. Bartling, Sunnyvale, CA (US); and Jafar Savoj, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 17, 2023, as Appl. No. 18/319,421.
Claims priority of provisional application 63/376,208, filed on Sep. 19, 2022.
Prior Publication US 2024/0097874 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 23/02 (2006.01); H04B 1/04 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01)
CPC H04L 7/0029 (2013.01) [H04B 1/04 (2013.01); H04L 7/033 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a front-end circuit configured to generate an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
a sample circuit including a first plurality of analog-to-digital converter circuits and a second plurality of analog-to-digital converter circuits, wherein the first plurality of analog-to-digital converter circuits are configured to sample, using a recovered clock signal, the equalized signal at times corresponding to odd-numbered data symbols of the plurality of data symbols to generate a first plurality of samples, and wherein the second plurality of analog-to-digital converter circuits are configured to sample, using the recovered clock signal, the equalized signal at times corresponding to even-numbered data symbols of the plurality of data symbols to generate a second plurality of samples; and
a recovery circuit configured to process the first plurality of samples and the second plurality of samples to generate a plurality of recovered data symbols.