US 12,244,518 B2
Network-on-chip architecture for handling different data sizes
Krishnan Srinivasan, San Jose, CA (US); Sagheer Ahmad, Cupertino, CA (US); Ygal Arbel, Morgan Hill, CA (US); and Aman Gupta, Sunnyvale, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on May 13, 2022, as Appl. No. 17/663,376.
Prior Publication US 2023/0370392 A1, Nov. 16, 2023
Int. Cl. H04L 49/109 (2022.01)
CPC H04L 49/109 (2013.01) 17 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a Network-on-Chip (NoC) including:
a plurality of first interface circuits;
a plurality of second interface circuits; and
a plurality of switches, wherein the plurality of switches are interconnected and communicatively link the plurality of first interface circuits with the plurality of second interface circuits;
wherein the plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths;
wherein each switch of the plurality of switches includes a first sub-switch and a second sub-switch coupled to the first sub-switch by a synchronization channel; and
wherein one or more groups of complementary ports of the first sub-switch and the second sub-switch operate independently in a first operating mode of the different operating modes to convey data of a first width and operate cooperatively as a group in a second operating mode of the different operating modes to convey data of a second width greater than the first width.