| CPC H04L 43/10 (2013.01) [H04L 47/2483 (2013.01)] | 20 Claims |

|
1. A networking device comprising:
a packet processing pipeline circuit configured to implement a data plane; and
a hardware clock circuit,
wherein the packet processing pipeline circuit and the hardware clock circuit are configured to send a plurality of heartbeat packets on multiple paths to a second networking device, wherein the heartbeat packets are sent within a heartbeat period, and each of the heartbeat packets has a unique packet five tuple that includes an internet protocol (IP) address of the second networking device, and
wherein the networking device is configured to place packet header vectors (PHVs) for the heartbeat packets on an ingress queue of the data plane in response to receiving a heartbeat trigger signal.
|