| CPC H04L 1/1864 (2013.01) [H04L 1/189 (2013.01); H04L 1/1896 (2013.01); H04L 5/0044 (2013.01)] | 30 Claims | 

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               1. An apparatus, comprising: 
            one or more processors; 
                one or more memories coupled with the one or more processors; and 
                instructions stored in the one or more memories and executable by the processor one or more processors to cause the apparatus to: 
              receive a message indicating a decoding order for a user equipment (UE) to decode a first plurality of repetitions of a data transmission, iteration instructions indicating a quantity of iterations to perform on the first plurality of repetitions, or a combination thereof; 
                  monitor for one or more repetitions of the first plurality of repetitions; and 
                  transmit a feedback message based at least in part on decoding the one or more repetitions of the first plurality of repetitions or iterating the one or more repetitions of the first plurality of repetitions in accordance with the decoding order, the iteration instructions, or any combination thereof. 
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